The invention concerns the operation and architecture of a linear half-rate phase detector, and more particularly concerns a half-rate phase detector for a phase-locked loop which produces a linear phase difference output signal by combining signals indicative of the phase relationship between a recovered clock signal and a received non-return to zero (NRZ) data signal, with a delayed version of the NRZ data signal.
Phase synchronization and clock recovery, an important component of digital communications, is a manifold process by which a receiver is synchronized to an incoming signal in order that the receiver be enabled to reliably extract clock information from the input signal. One communication component used for such synchronization is the phase-locked loop (PLL). In NRZ signaling schemes, a PLL is a servo loop which compares a version of a clock signal embedded in the NRZ signal with a version of the clock signal synthesized from the incoming signal by the PLL. The PLL operates to measure and correct phase difference between the two clock signals. A typical PLL architecture with a frequency aided acquisition loop is illustrated in FIG. 1.
In FIG. 1, a PLL 100 includes a frequency detector 102 and phase detector 103 as would be found, for example, in a digital receiver. The PLL 100 further includes a loop filter 104, voltage controlled oscillator (VCO) 106 and frequency divider 109 with division value N. The PLL has an input 110 to receive a divided-down clock signal (VCODIVCLK) and an input 111 to receive a reference clock (RCLK), which aid in a frequency acquisition process. For phase acquisition, the PLL has two inputs, 112 and 113, for respectively receiving an incoming data signal (DATA) and a synthesized clock signal (CLK) recovered by the PLL 100 from the incoming data signal. The frequency acquisition process is conducted as follows. The frequency detector 102 receives RCLK and VCODIVCLK (the clock output of the VCO 106, divided by N) as inputs. The frequency detector 102 has UP and DOWN outputs. If the frequency of VCODIVCLK is higher than the frequency of RCLK, the average of the UP-DOWN outputs is negative. If the frequency of VCODIVCLK is lower than the frequency of RCLK, the average of the UP-DOWN outputs is positive. The UP-DOWN outputs are averaged by the loop filter 104. In response to the UP-DOWN outputs, the loop filter 104 generates a voltage signal Vcontrol that controls the response of the PLL 100 to indicated errors in frequency difference measured by the frequency detector 102. The VCO 106 produces the CLK signal at a frequency determined by the voltage level of the Vcontrol signal. The condition where the average of the UP-DOWN outputs is zero is referred to as “frequency lock”. At frequency lock the frequency of the CLK signal is exactly “N” times the frequency of RCLK. When frequency lock occurs, control of the frequency/phase lock process is passed to the phase detector 103, which operates to acquire phase lock between the DATA and CLK signals, and to extract clock signal information from the DATA signal. In operation, the phase detector 103 produces a phase synchronization signal (PHASE) and a data reference signal (REF). The PHASE signal indicates the degree and direction of any phase difference between the DATA and CLK signals. The REF signal indicates the degree of synchronization between a data pattern, or symbol interval in the DATA signal and a corresponding integration interval in the PLL. The REF signal provides a reference comparison for the PHASE signal for different data patterns in the DATA signal. In a phase acquisition lock condition, the phase detector 103 produces a net average zero signal, wherein PHASE−REF=0. The loop filter 104 receives the PHASE and REF signals and generates the voltage signal Vcontrol in response thereto. The Vcontrol signal controls the response of the PLL 100 by indicating errors in phase between the DATA and CLK signals as measured by the phase detector 103. The VCO 106 produces a synthesized recovered clock signal (CLK) on an output 108 that is aligned with the phase of the DATA signal (“phase aligned”) at a frequency determined by the voltage level of the Vcontrol signal. The CLK signal is provided to the input of the frequency divider 109, which divides it by N to produce VCODICCLK. The output is also connected to the input 113 of the phase detector 103 in order to provide the CLK signal as an input to the phase detector 103. The phase detector 103 also responds to the DATA and CLK signals by extracting data from the DATA signals and providing the extracted data as a RECOVERED DATA signal on output.
The phase detector 103 of the PLL 100 may be practiced as a prior art phase detector 200, illustrated in FIG. 2. Although illustrated as a discrete, or stand-alone apparatus comprising a combination of elements, the prior art phase detector 200 (and the novel phase detector later described) would preferably be found as a component of an integrated circuit (IC), often, although not necessarily, in combination with a frequency detector, manufactured using semiconductor technology, and intended for use in an integrated electronics appliance such as a receiver.
The phase detector 200 is a high-speed linear half rate phase detector. In this regard, it is high-speed in that it must be able to respond to pulse signals having pulse widths that may be as narrow as a few tens of picoseconds. The phase detector is said to be “half rate” in that the CLK signal is equal in frequency to the fundamental rate of the DATA signal. In this regard, there are “full rate” phase detectors that operate at twice the rate of an incoming data signal. These full rate phase detectors are manufactured using exotic semiconductor process technologies that produce very high speed devices capable of responding to pulse signals having pulse widths that are less than ten picoseconds wide; however, such devices use non-standard process technologies and are very expensive to integrate with standard process technologies. Half rate phase detectors, on the other hand, are manufactured using standard process technology. A linear half rate phase detector may have an architecture that is easy to integrate with larger chips while still delivering optimum speed and power performance comparable to full rate phase detectors.
Referring to FIG. 2, the phase detector 200 detects a phase difference between the DATA signal and the CLK signal recovered from the DATA signal. The phase detector 200 includes a first latch 202 and a second latch 204. A latch is a data storage device that samples an input signal in response to a clock signal. In this regard, each of the latches 202 and 204 has an input (D) for a data signal, a input (CLK) for a clock signal. The output (Q) of each latch is enabled by a first transition of a CLK input such that the signal on the output follows (“samples”) the signal at the latch's input until the CLK input transitions at the transition (the second transition) immediately following the first transition. Following the second transition, the output stays at the level the input signal had at the second transition. The output of the first latch 202 is connected to a first input of a first exclusive-OR (XOR) gate 205, and to the input (D) of a third latch 206. The output of the second latch 204 is connected to a second input of the XOR gate 205, and to the input (D) of a fourth latch 208. The first XOR gate 205 produces the PHASE signal at its output. The output (Q) of the third latch 206 is connected to a first input of a second XOR gate 209, and to the input of a buffer 210. The output (Q) of the fourth latch 208 is connected to a second input of the second XOR gate 209, and to the input of a buffer 211. The second XOR gate 209 produces the REF signal at its output. The data in the incoming DATA signal is produced, in differential form, at the outputs of the buffers 210 and 211. Although the circuit architecture of the phase detector 200 depicted in FIG. 2 is single-ended, those skilled in the art will appreciate that corresponding circuit architecture could be deployed in differential form.
The operation of the prior art phase detector 200 is represented by the waveforms of FIG. 3. In FIG. 3, the labels on the several waveforms correspond with identical labels at various locations in the phase detector 200 of FIG. 2 and represent the waveforms of signals at those locations. The CLK1 signal that is provided to the CLK inputs of the first and fourth latches 202 and 208 may be derived, for example, from the CLK of the PLL 100 of FIG. 1. The inverse of the CLK1 signal is provided to the CLK inputs of the second and third latches 204 and 206. When phase lock occurs, one of the transitions of the CLK1 signal is centered in a bit of the DATA signal. The half-rate architecture of the phase detector 200 uses the opposite transitions of the CLK1 signal in the first and second latches to sample the input DATA signal in the latches 202 and 204, causing the production of a signal Q1 at the output of the first latch 202 and a signal Q2 at the output of the second latch 204. The Q1 and Q2 signals are precursors to the REF signal. The PHASE signal is generated by combining Q1 and Q2 signals in the first XOR gate 205. Similarly, the opposite transitions of the CLK1 signal are used to sample the outputs of the first and second latches, with their respective outputs Q3 and Q4 combined by the second XOR gate 209 to produce the REF signal. As shown in FIG. 3, the precursor signals Q1 and Q2 used to generate the REF signal exhibit minimum pulse widths when the DATA signal transitions at its highest possible rate. The minimum width pulse 212 of Q1 is generated by transition 210 of CLK1 signal and transition 208 of DATA signal. The minimum pulse width 213 of Q2 is generated by transition 211 of CLK1 signal and transition 209 of DATA signal. The first XOR gate 205 must respond to these minimum widths in order to faithfully track the difference in phase between the CLK signal and the incoming data signal. However, when these minimum widths begin to approach tens of picoseconds in width, the linear response of the first XOR gate 205 is severely degraded, limiting the linearity of the PHASE outputs in reaching full DC level for different DATA patterns. This contributes to phase offset errors and data pattern dependent phase offsets. This limitation on the performance of the XOR gate leads to an advancing reduction in the accuracy with which the PHASE signal represents the actual phase difference being measured. This limits the linear range of operation and the jitter tolerance of the half-rate phase detector 200.